UPS is for short of Uninterruptible Power Supply. Because when the power supply shuts down, it will switch to the inversion status quickly, to prevent the working computers from losing important documents due to the unexpected power off, and fail to save. It is not used as backup power. If you are just willing to use while power off, an inverter will do. Mostly in home UPS system, it is always maintenance free type lead acid battery. In ideal conditions, to extend the battery life, is to keep the battery in “floating charge” status or constant voltage charge status.
Charge Voltage 2.275V/Cell
Charge Temperature 20℃
Discharge Temperature -15℃- +50℃
1. While in floating charge, please use voltage at 2.275V/Cell(20℃ condition value), to do constant voltage charge or constant current charge under 0.002CA. When the temperature under 0℃ or over 40℃, it is necessary to adjust the charging voltage, take 20℃ as a start point, temperature changes 1℃, single cell voltage adjust -3mV.
2. While in cycle charge, charging voltage as 2.40-2.50V/Cell(20℃ condition value), to do constant voltage. When the temperature under 5℃ or over 35℃, take 20℃ as start point, temperature charges 1℃, adjust -4mV/Cell.
First period, charging current is under 0.25CA.
The temperature(under 5℃) lower, charging time is longer. The temperature(over 35℃) higher, it is easily to get over charged. So especially when cycle use, it is better to charge between 5℃ to 30℃.
To avoid over charge, it is necessary to install charge timer, or automatically change into trickle charge status.
The temperature should be managed between -15℃ to 40℃.
The temperature should be managed between -15℃ to 50℃ while discharge.
Constant discharge current should be under 3CA (managed to be under 6CA)
Discharge end voltage changes according to current, generally as below. Note that the voltage cannot be lower than below voltages.
After discharge, please charge back in a short time. If over discharge occasionally, please charge back immediately.
Discharge Current Discharge End Voltage
Under 0.2CA 1.75V/Cell
0.2CA – 0.5CA 1.70V/Cell
0.5CA – 1.0CA 1.55V/Cell
Over 1.0CA 1.30V/Cell
Please follow below instructions when install batteries.
1.1 DO NOT install battery in a sealed room or near fire, or it is risky to cause explosion or fire disaster.
1.2 DO NOT use vinyl type film, which is easy to cause static electricity, to cover the battery. It is risky to cause explosion when static electricity occurs.
1.3 DO NOT install the battery wherever might water come in, or else it may cause electric shock or fire disaster.
1.4 DO NOT install the battery beyond -40℃ to 60℃ environment.
1.5 DO NOT use battery in a dusty environment, or it will cause short circuit.
1.6 Take care of the ventilation when install the battery in cabinet.
1.7 DO NOT use stick or label cover the top cover. There is gas leak under the top, the gas generated from battery inside will not escape.
1.8 Quantity in parallel – While in floating charge, plug-in type terminal battery only allowed using 3 rows. Screws type no limit, but more stable if less in parallel. Besides, while in parallel, it is necessary to consider the connector resistance same. As to keep the balance in different battery rows, please do not use over 3 rows in field.
1.9 Use different capacity, old or new, different factory produced batteries, as their performance difference may cause the electric appliance broken. Please avoid this situation.
1. Storage temperature should be between -20℃ to 40℃.
2. Storage battery should be fully charged status. Due to energy loss in transportation or storage, please recharge before use.
3. For long time storage, as to make up the self-discharge, please recharge.
Please avoid to storage the battery under 40℃ condition, as it is bad effected to the battery.
4. Please storage under dry, low temperature, good ventilation environment.
5. If battery package is wet while in transportation or storage, please remove the package immediately or it will cause battery discharge or burn terminals.
1. Check the batteries timely, if there is any dust or dirty condition, please use water wet cloth to remove the dirt. DO NOT use organic solvent such as gasoline or banana oil, chemic fabric is also not allowed.
2. While in float charge, the total voltage or meter voltage is under the standard voltage, should find the reason and handle the problem.
UPS Battery – Battery Life
Even UPS uses same battery technology, different factory produced battery lives a lot different. This is very important to end customer, because battery cost is very high (approx. 30% of UPS sale price). Battery problem will cause system stability, which is very annoying.
Temperature has big influence to the battery natural aging. Detail experimental data shows that every increase of 5 degree, battery life reduces 10%. So UPS should be design to keep the battery life. All online type and backup/online hybrid produce more heat than backup type and this is an important reason why backup type UPS is in a longer cycle of battery replacement.
Battery charger is a very important part of UPS system. Batteries’ charge condition has big influence on battery life. If the battery is always under constant voltage or “floating charge” condition, then its life could be highly increased. In fact, charging status battery life is much longer than storage status. Because charge can suspend battery natural aging progress, keep battery in charging whether UPS running or not.
Battery is made up of single “original unit”, every single unit is 12V. Original units in string to make higher battery pack, one 12V battery is made up by 6 single original cells, 24V battery is made up of 12 pieces single original cells, etc. When UPS battery is in charge, every original unit will be also charged. A little difference in performance will cause some original units’ voltage is higher than others; these units will age in advance. Then if one battery unit performance low down, the whole battery pack performance will low down. Experiments shows battery life is related with string quantity, battery voltage higher, aging faster. At a certain UPS battery capacity, battery voltage is better to be designed lower, at this condition, batter life the longest. Some factories’ UPS battery voltage higher, it is because when capacity confirmed, voltage higher, current lower, then choose thinner wires and lower power semi-conductor, then reduce UPS cost. 1KVA UPS battery voltage is always at 24V to 96V.
In ideal condition, to extend UPS battery life, should keep the battery always in floating charge status or constant voltage status. At this condition, battery will absorb very small charging current; it is called floating or self-discharge current. Although battery manufacturers recommended, some UPS design to make the battery afford extra small current, which is called ripple wave current. Ripple wave current is produced when battery supply constant current to inverter, according to conservation of energy, inverter has to input DC current to produce AC current. In this situation, battery made a small cycle, frequency is double as the output frequency.
Common backup type/ online type or backup/ ferromagnetic UPS will not produce ripple wave current, other design UPS will make various ripple wave currents. It can be known by checking the UPS structure drawing.
If UPS battery is between the charger and inverter, then battery will have ripple wave current. This is common double switch UPS.
If use pick-off diode, relay, converter, or rectifier to separate the battery and inverter, then battery will not produce ripple wave current.
Battery the least stable part in UPS system, UPS design directly affects battery stability. Keep the battery always in charging status (even if UPS down), will extend battery life. Avoid choosing high voltage UPS, some UPS design will produce ripple wave current, made extra over heat. Mostly battery in similar condition, but different design will apparently affect battery life. One unit battery is 12V, UPS need 96V, which means 8 units. Server 780W, 20% bonus, approx. 1000W, 2 hours, single unit is 20AH; we can choose 8 units rated capacity at 24AH.
There are various brand, most people choose local manufacturer, legal factory, quality assurance, long life span, cost-worthy.
UPS Battery – Charge Time
To a backup battery, when battery in power supply, the time to charge to full, is always no less than 24 hours; To cycle use battery, if previous discharge power and charge current are known, the charge time could be calculated by below formula at 25℃ condition.
UPS battery common terms
1. Over Discharge: continue discharge when battery voltage under end voltage
2. Recover Charge: prepare for next discharge, charge the battery to recover capacity
3. Over Charge: continue charge after fully charged status
4. Full Discharge: discharge battery to end voltage according to stipulated current
5. Nominal Voltage: means battery normal voltage in use, always a little lower than initial voltage
6. Cycle Service System: use method of discharge after full charge as a circle
7. Maximum Discharge Current: max current battery can discharge, in condition of no distortion, abnormal appearance, or pole fusing.
8. Self Discharge: battery capacity leak reduce, in no out power supply condition
9. Nominal Capacity: at standard temperature, discharge current and end voltage condition, amp hour energy can supply by fully charged battery
10. Hour Rate: time rate according to constant discharge current to end voltage, always use hour as unit to indicate battery capacity.
11. Actual Capacity: battery actual capacity according to a certain hour rate.
12. Trickle Charge: to make up for battery self-discharge, in no load condition, constant small charge current to charge.
13. Floating Charge: battery and load connect to rectifier charge in parallel, charge keeps charging to battery at a stable voltage. When it is power off, or load changes, battery can supply power directly to load without interruption.
14. Constant Voltage Charge: the charge method of keep stable voltage between terminals.
15. Constant Current Charge: the charge method of constant charge current
16. Stand-by Use: always in charge status, floating charge or tickle charge, in case of emergency.
17. Internal Resistance: battery inside total resistance
18. Cut-off Voltage of Discharge: end voltage according to different discharge current and battery types
19: Capacity Conservation Performance: after battery fully charged, the remain capacity after a certain time in open circuit status
20. Internal Short-Circuit: inside battery, positive and negative plates short circuit
UPS battery is one important part of UPS power supply, if battery not installed after purchase, please note below in storage:
(1) DO NOT storage battery in temperature beyond -20℃ to +50℃.
(2) Storage battery should be fully charged status. Due to energy loss in transportation or storage, please recharge before use.
(3) For long time storage, as to make up the self-discharge, please recharge.
Please avoid to storage the battery under 40℃ condition, as it is bad effected to the battery.
(4) Please storage under dry, low temperature, good ventilation environment.
(5) Battery performance decays in storage, please arrange usage in short time.
(6) If battery package is wet while in transportation or storage, please remove the package immediately or it will cause battery discharge or burn terminals.
(7) Check the batteries timely, if there is any dust or dirty condition, please use water wet cloth to remove the dirt. DO NOT use organic solvent such as gasoline or banana oil, chemic fabric is also not allowed.
UPS battery pack replacements is using reversal stop character of diode, make voltage difference between new pack and old pack manually. When new battery in, old battery out, use diode as electrical switch, supply power to DC main line instantly, avoid the battery voltage difference produce circle current, ensure the stability of DC power supply. In the meantime, avoid the unsafe factor due to the main line no power supply in battery switch procedure.
The method is:
1. Charger 2#U stop running, remove UPS battery pack GB’ fuse FU.
2. Connect diode (2CZ 200A/800V) to A & C terminals of fuse FU5.
3. Check connection complete, then recover fuse FU.
4. Remove fuse FU5, diode V connect in circuit, combine SA3, check negative – WOM voltage is approx. 241V, positive – WOM voltage approx. 218V, diode reverse cut-off. Main line is powered by charger 1#U, battery pack GB, and GB’. As battery pack GB’ voltage lower, DC load powered by charger 1#U, battery pack GB.
5. Disconnect SA1, remove fuse FU3, FU4, Battery pack GB’ instantly supply power to main line through diode V.
6. Run charge 2#U, adjust voltage to nominal, main line is powered by charger 2#U, battery pack GB’ in parallel.
7. Remove old battery pack GB, connect positive and negative wires to charge 1#U positive &negative terminals.
8. Run charger 1#U, make it and old battery pack in parallel, voltage 241V.
9. Stop charger 2#U, battery pack GB’ voltage low down to 235V in a short time.
10. Combine SA1, charger 1#U, old battery pack GB, new battery pack GB’ in parallel, power supply to main line.
11. Disconnect SA3, remove new battery pack GB’.
12. Connect diode V to FU3.
13. Insert FU4, charger 1#U, new and old battery pack power supply to main line.
14. Disconnect SA1, new and old battery pack power supply to main line through diode V.
15. Install fuse FU3, diode V is short. Now diode is now longer useful, remove it.
16. Remove old battery pack.
17. Connect SA1, charger 1#U and new battery pack, power supply to main line in parallel.
Use in marine equipment, cable television, emergency lighting system, backup power supply, large UPS and computer backup power plant, electric wheelchair, golf cart, electric fork lift, trail system, power plant, electricity system.
In SiO;or other intermediate layers are deposited with Si HCH by atmospheric pressure chemical vapor deposition APCVD, which is a conventional process in the microelectronics field.The reaction chamber and process described in Section 2.4.3 are applicable to heterogeneous substrate crystalline silicon thin film solar UPS BATTERY. Polysilicon layer is deposited on Si substrate plated with SiO 2, and then ZMR is recrystallized by zone melting to form seed layer.The Si layer before ZMR is etched preferentially and has obvious dense grain boundaries in its cross section.The SiO 2 layer is closed and smooth. The seed layer grown by APCVD and ZMR has no voids or other harmful defects except grain boundaries.
Such research results can be transferred to a suitable ceramic substrate.The smooth surface of the SISIIC ceramic substrate is covered with an intermediate layer and a seed layer which are free from damage and also smooth.In order to ensure a successful seed layer deposition, there are certain requirements for the intermediate layer, and the surface of the intermediate layer cannot be contaminated by metal impurities.This will form local eutectic of metal silicide, causing whisker growth [ 122 ] eutectic refers to the simultaneous formation of two different solid phases from one liquid phase during solidification, while whisker growth refers to the metallurgical phenomenon of spontaneous growth of tiny filamentous hair from the semiconductor or metal surface.
The intermediate layer needs to have a uniform surface without voids.Otherwise, preferential growth rate will form non-uniform regions of Si film or substrate impurities will cause whisker growth.
When the Si layer is deposited on the improper rough and porous Celeron Si AlON ceramic substrate, the surface of Si AlON substrate reacts chemically with the ONO interlayer, destroying the structural integrity and forming cracks, thus causing whisker formation during Si deposition.Scanning electron microscope ( SEM ) is a common electron microscope, which scans the surface of a sample with a grating pattern through a high-energy electron beam and forms an image.Electrons interact with the atoms that make up the sample, and the resulting signals contain information such as the surface morphology, composition and conductivity of the sample.
Epitaxial growth on the ZMR seed layer will also encounter a similar situation.If the surface of the seed layer deviates from the ideal state ( closed, low defect density, clean ), epitaxial growth will not be ideal.Since ceramics often contain metallurgical grade raw materials, it is not easy to clean the seed layer on the ceramic substrate / interlayer before epitaxial growth.During the wet chemical cleaning of the sample, cross contamination of the surface of the seed layer will occur, resulting in whisker growth or increased defect density during epitaxial growth.If the substrate is porous, wet chemical defects are more difficult for safety reasons.Cross contamination also occurs during high temperature epitaxial growth, and impurities diffused from the substrate are transported to the grown Si layer by gas phase.
These effects are only minor, and the epitaxial layer still has good quality.If the seed layer is not closed or the thermal expansion coefficient tec of the substrate and si layer does not match, epitaxial growth will encounter greater problems.When the middle layer is not covered by the seed layer and the seed layer is not closed, the epitaxial layer will have a polycrystalline silicon region with fine grain size.Such cracks can cut off the lateral conductivity of the epitaxial layer and form shunt resistance between the metallized emitter and base in the solar cell fabrication process.
To sum up, Si deposition on ceramic substrates can, in principle, use the mature CVD technology in the microelectronics industry.The quality of the Si layer is directly related to the quality of the substrate: substrates with more defects will lead to Si deposited films of poor quality.Impurities, voids or cracks in the intermediate layer and seed layer can induce cracks, whiskers and even other growth defects such as polycrystalline growth during epitaxial growth.
Heterogeneous substrate crystalline silicon thin film solar cell
In principle, the solar cell process for epitaxial Si thin films prepared at a maximum temperature of 1400 C is straightforward: all mature technologies of crystalline silicon solar UPS BATTERY can be applied to the preparation of heterogeneous substrate crystalline silicon thin film solar UPS BATTERY.But.The use of heterogeneous substrates may render some process steps unsuitable.We will first discuss the principle requirements of appropriate solar cell technology and its experimental results, then summarize the influence of hydrogen passivation and zone melting recrystallization scanning speed on the open circuit voltage on the model substrate, and demonstrate the feasibility of preparing large-area heterogeneous substrate crystalline silicon thin film solar cell. Finally, we describe the influence of ceramic substrate crystalline silicon thin film solar cell and substrate / Si layer system on solar cell performance.
Solar cell technology
The biggest advantage of preparing a heterogeneous substrate crystalline silicon thin film solar cell at high temperature is its compatibility with the traditional solar cell process, because the active layer containing polysilicon is similar to the traditional polysilicon silicon wafer.Typical cross-sectional structure and process flow of heterogeneous substrate crystalline silicon thin film solar UPS BATTERY.Since the middle layer and the ceramic substrate are both insulators, the emitter contact and the base contact are both prepared on the front surface of the solar cell, and the P - type base has a frame contact design.Similar to the traditional silicon wafer, it is necessary to prepare emitter by diffusion, deposit antireflection film to reduce reflection loss, and prepare metal contacts to ensure current separation from the UPS BATTERY.Before evaporating or plating the emitter / base contact, photolithography is required to determine the location of the emitter / base contact and reactive ion etching is required to separate the base from the emitter.The last two steps of the process flow are to carry out remote plasma hydrogen passivation ( RPHP ) and deposit a double layer antireflection coating ( DL ARC ).
Compared with the traditional process of crystalline silicon solar UPS BATTERY, the following processes are particularly important for heterogeneous substrate crystalline silicon thin film solar UPS BATTERY:
Front surface texture: The combination of front surface texture of epitaxial layer and refractive index difference of seed layer / interlayer interface can realize effective light trapping structure ( see 220.127.116.11 Section ).By using the traditional wet chemical alkaline anisotropic etching, irregular pyramid structures can be formed on the front surface of the epitaxial layer, thus improving the conversion efficiency of the heterogeneous substrate crystalline silicon thin film solar cell.Alkaline texturing can easily achieve > 90 % internal reflectivity, however, texturing with KOH / isopropanol will lose up to 10 pan of si layer.The loss of Si in the texturing process is equivalent to 1 / 3 of Si deposition, thus greatly increasing the cost of the heterogeneous substrate crystalline silicon thin film solar cell.One alternative to alkaline texturing is plasma texturing, which will be described below.
Passivation of front surface: Compared with the traditional crystalline silicon solar cell, the thickness of Si thin film is limited, and the combination of front surface and back surface has a more serious impact on the performance of the solar cell.The back surface field BSF formed by high and low junctions can effectively reduce the surface recombination of the back surface.In principle, thermal oxidation or deposition of SiN can passivate the front surface.However, up to now, no systematic research on passivation of the front surface of ceramic substrate crystalline silicon thin film solar UPS BATTERY has been reported.
Passivation in vivo: hydrogen purification can eliminate in vivo defects, which is good for ZMR seed layer and can improve the performance of heterogeneous substrate crystalline silicon thin film solar cell ( see 18.104.22.168 section ).There are mainly two ways to increase H atoms required for passivation: forming H plasma in the furnace loaded with samples, or providing H atoms directly from SiN: H antireflection film.Up to now, only the first method has been reported to be applied to ceramic substrate crystalline silicon thin film solar UPS BATTERY.
Although in principle almost every traditional solar cell process can be applied to heterogeneous substrate crystalline silicon thin film solar UPS BATTERY, the use of ceramic substrates can cause some serious problems.A certain porosity is one of the most important problems: if the ceramic has a certain open porosity, the wet chemical process will be difficult and sometimes even dangerous.Chemical substances used in etching or electroplating will fill the pores. Due to the large internal surface area, rinsing the wafer with clean water will not remove the chemical substances in the pores, and hazardous chemical substances will gradually diffuse and have a harmful effect on subsequent process steps.Therefore, some solar cell processes need to be developed to cope with this special situation.At present, there are two strategies: the first is to seal the development pores.For example, a thicker intermediate layer is deposited or coated with a resin capable of resisting various chemicals in the process.All open pores in the graphite substrate coated with SiC seed layer are closed [ 12 ].If resin is used as an additional layer in a large area, the cost of the process of sealing open pores will be too high.The second strategy is to use a dry process, especially a plasma etching process.Plasma etching is a mature technology, and its application in crystalline silicon solar UPS BATTERY has also attracted great interest [ 123 \ A research team has attempted to apply plasma etching process to ceramic substrate crystalline silicon thin film solar UPS BATTERY.If F - containing plasma is used, each problematic wet chemical etching step can be replaced by N24 - 126 ]:
removing the covering layer after the zone melting recrystallization ZMR;
preparing a surface before epitaxial growth;
Clean the surface before emitter diffusion;
Texturing with less Si loss;
removing phosphosilicate glass;
Si etching to form trenches.
However, a low-cost ceramic-based heterogeneous substrate crystalline silicon thin film solar cell produced entirely by dry process is not a conventional process.
If the substrate and the intermediate layer are electrically insulated, other more complex solar cell processes are required.Trenches need to be scored or etched on the Si layer to achieve one side contact, i.e. metal contacts of the base and emitter are located on the front surface of the solar cell.If one-side contact is not needed, the strip batteries need to be integrated and interconnected.Several research teams have used single-side contact as a routine process, while only a few authors reported on integrated interconnection [ 127 - 13 ].Due to the different growth rates caused by different crystal orientations, the surface of the epitaxially thickened ZMR layer is relatively rough, which poses a challenge to the realization of a better integrated interconnection process.Rents ch et al reported on the difficulties faced by integrated interconnection [ IZ7 ].When attempting to metallize the integrated interconnection on the epitaxially thickened ZMR layer by screen printing, a local shunt path will occur.In addition to screen printing, other integrated interconnection concepts studied include:
Scouring grooves and metal drop coating [ 128 ];Shadow mask evaporation 1 30 ];Bow I Wire Bonding [ M ] 0
Brendel et al. proposed the concept of metal-free integrated interconnection, i.e. metallization on the base and emitter epitaxial layers by special shadow mask evaporation [ 132 ].Except for the scribing grooves and metal drop coating processes reported by SIMS and others, these concepts of integrated interconnection are not mature enough to achieve cost-effective mass production.After the integrated interconnection is prepared by the scribing groove and metal drop coating process, the ceramic substrate crystalline silicon thin film solar cell forms a 5.6cm2 area module integrated with four UPS BATTERY, the conversion efficiency can reach 5.6 %, and the open circuit voltage I can reach 2.2V ..
Gaz Uz et al also published a model substrate crystal silicon thin film solar cell 86 cm2 large area module with good conversion efficiency, which is composed of nine UPS BATTERY strips, the conversion efficiency reaches 6.3 %, and the open circuit voltage of each UPS BATTERY reaches 544 mV.
To sum up, because the ceramic substrate has many pores, the wet chemical etching process will bring many problems to the solar cell process of the ceramic substrate crystalline silicon thin film solar cell.For solar cell production with high production rate, only a dry process such as plasma etching can give a better solution to this problem.
Model substrate crystalline silicon thin film solar cell
The scanning speed of zone melting recrystallization and remote plasma hydrogen passivation have been reported much more on model substrate crystalline silicon thin film solar UPS BATTERY ( see 22.214.171.124 section for definition ) than on heterogeneous substrate crystalline silicon thin film solar UPS BATTERY.The study of model substrate crystalline silicon thin film solar cell can give important information of zone melting recrystallization ZMR layer.Japanese mitsubishi electric ( see Section 2.3.1 ) reported that the ZMR layer on the oxidized silicon wafer realized the ideal conversion efficiency of the model substrate crystalline silicon thin film solar cell: the conversion efficiency of the 1cm x 1cm area cell reached 16.45 % [ 66 ], while the conversion efficiency of the 10cm x 10cm area cell reached 16 % [ 67 ].The solar cell technology for the two cell applications is very complex, but the results confirm the great potential of developing heterogeneous substrate crystalline silicon thin film solar UPS BATTERY.
In order to achieve such a result on a more cost-effective substrate, several parameters and conditions of the process for preparing ZMR layer have been systematically studied.When a low-cost Si substrate ( such as a powder grown silicon SSP ) is used, better results can be easily transferred, while the case of ceramic substrates is more difficult.
In the following, we will discuss in detail two factors that can optimize the performance of the model substrate crystalline silicon thin film solar cell: the scanning speed of zone melting recrystallization ZMR and the scanning speed of RPH PO passivated by long-distance plasma hydrogen are the most important cost parameters of ZMR process. The experiment of defect density raises a question: what defect density can get the best performance of the model substrate crystalline silicon thin film solar cell ( see 126.96.36.199 section )?The mitsubishi electric research team observed that increasing the scanning speed and defect density will greatly reduce the performance of solar UPS BATTERY ( mainly the open circuit voltage ) [ 6 <' 91,96 ].The research team of FHG - ISE at Hoff Solar System Research Institute in Flawn confirmed this conclusion about scanning speed.However, FHG - ISE research team also confirmed that RPHP treatment can increase VOE and short-circuit current density JGN of the model substrate crystalline silicon thin film solar cell.The' improvement effect of samples with high scanning speed is better than that of samples with low scanning speed, while JSC improvement effect of samples with low scanning speed is better than that of samples with high scanning speed, so the conversion efficiency of samples with medium scanning speed is the largest.
Then in this experiment, two groups of solar UPS BATTERY were compared [ U3 ]:
In the first group of samples, the ZMR layer normally doped on the model substrate does not adopt epitaxial deposition and is directly subjected to solar cell technology.In the second group of samples, the highly doped ZMR seed layer on the model substrate is epitaxially thickened by normal doping, and then the solar cell process is performed.
The effect of RPHP on the performance of the model substrate crystalline silicon thin film solar cell can be evaluated by comparing before and after the first group of samples RPHP without epitaxial thickening.After RPHP, it has increased about 30mV, which is independent of ZMR scanning speed. The curve fitted by least squares still keeps a similar shape, but the value has increased a lot.For samples with higher scanning speed, RPHP seems to make the distribution of people at the same scanning speed more concentrated.The RPHP results agree with the EPD measurements described in the 188.8.131.52 section, confirming that the defect density is almost the same at any ZMR scanning speed and the defect can be passivated by RPHP.The change trend of ZMR also corresponds to the pit density ￠ 0: with the change of ZMR scanning speed, it will not change too much.When the scanning speed increases about 20 times from 20 mm / min to 350 mm / min, the average value of VOE decreases only about 15mV.Such a result is very meaningful because an important conclusion can be drawn that a high conversion efficiency solar cell can be prepared by Si layer obtained with high ZMR scanning speed.
If the first set of samples without an epitaxial layer and the second set of samples with an epitaxial layer are further compared.The curves are quite different:
At almost all ZMR scanning speeds, people with epitaxial layer samples are significantly lower.According to the 184.108.40.206 Festival, the EPD values differ by an order of magnitude compared with the results here.
The curve shape depending on ZMR scanning speed is obviously different.Only the ZMR layer curve saturates in the region with high ZMR scanning speed, while the cell with epitaxial layer decreases rapidly with ZMR scanning speed.
The research results here support the conclusion of the 220.127.116.11 Festival: in order to optimize the performance of the heterogeneous substrate crystalline silicon thin film solar cell, the concept of seed layer including epitaxial layer may not be the best design, especially in the case of high ZMR scanning speed.RPHP can increase the conversion efficiency by 5 % to 10 %, but still cannot offset the harmful effect of high defect density caused by epitaxial layers.
Through - hole etched film separation and laser sintering back-channel Japanese mitsubishi electric first developed a large area ( > 50 cm2 ) model substrate crystalline silicon thin film solar cell using the zone melting recrystallization ZMR process ( see 18.104.22.168 Section ).The technical route used is via hole etching thin film separation ( VEST ) and Si transfer by wet chemical process.The intermediate layer' separates the whole isi layer from the substrate and can be applied to the si layer with a thickness of about 80 [ 99 ]. the conversion efficiency of the obtained model substrate crystalline silicon thin film solar cell reaches 16.0 %., reber, etc. ( 10 ) recently published laser - fired back channel ( LFA ) technology.Unlike VEST, the Si layer using LFA still adheres to the substrate, forming a large area silicon wafer replacement after recrystallization.LFA brings the epitaxially deposited base layer into contact with the substrate wafer by sintering the laser via to the intermediate layer.Then, the standard solar cell process is used to metallize the front emitter and the back base to obtain a model substrate crystalline silicon thin film solar cell with better performance parameters:
Area 86 cm2;
Open circuit voltage VOC = 556 mV;
Short circuit current density JSC = 25.0 mA / cm2;
Fill factor FF = 60.7 %;
Conversion efficiency 7 / = 8.4 %.
Among them, the conversion efficiency is mainly restricted by the result of the high series resistance 0 LFA process caused by the improper design of the via hole pattern, which clearly proves the feasibility of the silicon wafer replacement concept.Through welding, the metal strip connects the front contact of the cell and the back electrode of the adjacent cell, and then is laminated and packaged into a small component, which is consistent with the traditional lamination process of crystalline silicon solar UPS BATTERY.The widget reached 3.2V, which is almost the sum of six silicon chip substitutes.
Ceramic substrate crystalline silicon thin film solar cell
Up to now, there are not many reports on the research results of fabricating heterogeneous substrate crystalline silicon thin film solar UPS BATTERY on ceramic substrates or low-cost Si substrates.The zone melting recrystallization ZMR uses graphite strip heater or linear halogen lamp as heat source, and the experimental results of high conversion efficiency of heterogeneous substrate crystalline silicon thin film solar cell are shown in actual .2.In the sample using electrically pure raw materials, the 302 - coated powder grows the SSP substrate with silicon, achieving the highest conversion efficiency of 11.3 %.In the samples using metallurgical grade raw materials, the silicon-impregnated silicon carbide SISIIC ceramic substrate achieved the highest conversion efficiency of 10.7 %.However, in these reports, the number of batch processes is small, with only about 20 batteries.Actual. 2 also does not give information on the appropriate degree of substrate.
We will discuss three kinds of ceramic substrate crystalline silicon thin film solar UPS BATTERY in particular.
Andalusite ceramic substrate: focusing on the role of light trapping structure;Si 3N 4 ceramic substrate: the influence of TEC that does not match the coefficient of thermal expansion on crack formation;Silicon - infiltrated silicon carbide ASIC ceramic substrate: the most appropriate substrate selection.
S 3.1 mullite ceramic substrate
Bour Dais et al reported a 1cm2 area ceramic substrate crystalline silicon thin film solar cell prepared by tape casting process on mullite ceramic substrate. The process flow is shown in the actual. 26.The mullite used is bright and white in color, and small grains in the body diffuse the light, which can form a good scattering back mirror when used as a substrate.Three selected samples demonstrate the effect of the active layer / intermediate layer design on the characteristics of the light trapping structure.Three different active layer / intermediate layer configurations are shown in actual .3.The corresponding external quantum efficiency EQE curve.However, the smooth Ono interlayer reduces the suede and internal reflection of bare mullite substrate.Therefore, compared with UPS BATTERY B, the Ono interlayer as a diffusion barrier layer reduces the influence of mullite substrate impurity diffusion on Si active layer and increases the number of people, but the smooth Ono interlayer also weakens the light trapping structure and reduces the comparison of the three samples, indicating that a reasonable light trapping structure is very important for ceramic substrate crystalline silicon thin film solar UPS BATTERY to achieve higher current.However, a method such as UPS BATTERY B to improve the light trapping structure on the other hand will reduce the electrical quality of the active layer and may cause more serious problems than electron collection.Therefore, any method for improving the conversion efficiency of ceramic substrate crystalline silicon thin film solar UPS BATTERY needs to comprehensively consider the harmful effects of this method on the characteristics of solar UPS BATTERY in other aspects.
silicon nitride ceramic substrate
Baum reported that Si3N4 ceramic substrate crystalline silicon thin film solar cell uses hot pressing sintering Si3N4 ceramic as substrate and is plated with Ono interlayer.Because the coefficient of thermal expansion 7Tc does not match, cracks in the Si layer are formed.The corresponding effective diffusion length distribution shows that.Cracks have a harmful effect on the performance of solar UPS BATTERY.Obviously, several triangular areas with very low lifetime are located in the corner of ZMR layer that should not be disturbed.In these triangular areas caused by deeper cracks, the base current can no longer flow to the border contact around the active layer.The quantum efficiency of these regions is also almost zero.Through more careful observation.It can be found that some white lines indicate an increased effective short-circuit current density, starting at the bottom edge of 1 = 6mm and connecting to the left in about a 45 direction.These lines are also cracks, but they are too shallow to electrically separate the base and do not affect carrier transport to the frame contact.The vertical emitter formed by the common diffusion process can effectively collect carriers within one diffusion length from the crack.In these regions, quantum efficiency is relatively high.However, the damage caused by cracks in the collection area is more serious than that caused by the vertical emitter, so the cracks formed by TEC mismatch will deteriorate the overall performance of Si 3N 4 ceramic substrate crystalline silicon thin film solar cell.
To sum up, the geometric integrity of Si layer is a basic requirement and one of the most important conditions for the development of high-quality heterogeneous substrate crystalline silicon thin film solar UPS BATTERY.It is necessary to select the appropriate ceramic as the substrate material through efforts.
Silicon - infiltrated silicon carbide ceramic substrate
The heterogeneous substrate crystalline silicon thin film solar cell prepared on silicon-impregnated silicon carbide SISISIC ceramics has good performance, indicating that SISISIC ceramics are very suitable substrate materials.SISISIC ceramics have almost no pores and a closed flat surface is ideal, which is suitable for standard solar cell processes including wet chemical etching.The process flow of solar cell is similar to the actual. 26.However, an additional thermal oxidation process is required to passivate the front surface.The reported characteristics of SISISIC ceramic substrate crystalline silicon thin film solar cell are:
Cell area 1cm2;
Open circuit voltage VOC = 554 mV;
Short circuit current density JSC = 28.9 mA / cm2;
Fill factor FF = 66.8 %;
The conversion efficiency is 10.7 %.
The internal quantum efficiency / QE curve as shown in the actual. 33 can give more information about the film and process quality: the relatively high IQE value of 400 nm confirms that the front surface thermal oxide passivation technology is effective.At 600 nm, the film has already started to decline, indicating that the film quality is not ideal due to impurity contamination.A small bump near 900 nm indicates a better light trapping structure.And the performance is relatively good JSC.
The histogram of the effective diffusion length leff of the sisic ceramic substrate crystalline silicon thin film solar cell has a wide distribution, ranging from 560 mm.Only a small fraction of LTFF measurements exceed twice the thickness of the 25 PIM base layer, i.e. 50 / " m ..The average value of Leff is 34 PTM, which is still higher than the base layer thickness.This once again confirms the effective effect of surface passivation and the relatively good crystal quality of the epitaxial layer.
Although SISISIC ceramic is the most suitable substrate material, strategies to further improve the conversion efficiency of SISIC ceramic substrate crystalline silicon thin film solar UPS BATTERY include:
reducing the thickness of the active layer so that the ratio of the average effective diffusion length to the thickness of the active layer reaches 2;Further improve the passivation of the front surface ( thermal oxidation or SiN, );Back surface field BSF ( higher doped BSF layer );
Using the back surface of tiny rough particles to improve the light trapping effect.
This chapter discusses in detail the research and development of heterogeneous substrate crystalline silicon thin film solar UPS BATTERY.Only a few research teams around the world focus on this low-cost substrate-based thin-film solar cell technology.The high temperature process discussed in this chapter has great potential to realize high conversion efficiency of solar UPS BATTERY and low cost of UPS BATTERY components.The general production process for heterogeneous substrate crystalline silicon thin film solar UPS BATTERY is based on a suitable substrate that is stable at high temperature ( > 1400 c ) and requires the deposition of intermediate layers ( SiO 2, sin, or sic ) on the substrate.A Si layer is formed on such a stack, then the Si layer is sealed with a SiO 2 capping layer, and then a zone melting recrystallization ZMR process is performed.ZMR process step is the key step to determine the technology of heterogeneous substrate crystalline silicon thin film solar cell, which can greatly increase the area of single crystal grain in deposited Si layer, up to 9 orders of magnitude.after removing the cover layer.The ZMR layer ( seed layer ) can be epitaxially thickened to form an absorption layer for solar UPS BATTERY.The main advantages of completing the stacking are the temperature stability and crystallinity of the Si layer, even reaching the level of the traditional polysilicon silicon wafer.
Most ZMR layer research is based on model substrate, i.e. silicon wafer plated with & 02.These substrates are particularly useful for parameter studies because they are highly reproducible.A lot of research progress has been made on the deeper understanding of the changes of high-speed recrystallization and chlorination characteristics of the samples.The model substrate crystalline silicon thin film solar cell without epitaxial growth after zmr has a higher open circuit voltage VW than the sample after zmr epitaxial growth as shown in actual .29 ..For samples without epitaxial growth after ZMR, the curve of W with respect to ZMR scanning speed gives a very important conclusion: when the scanning speed is in the range of 150400 MRN / min, people tend to be saturated.Therefore, the ZMR scanning speed and production rate can be further increased while ensuring the crystal quality.
In addition to the research based on model substrates, many kinds of ceramic substrates have been tested separately in recent years to find suitable heterogeneous substrates.Experiments show that.This study provides a basis for finding suitable ceramic substrate materials.Make the substrate manufacturer focus on researching and developing the most suitable substrate.Up to now, there are not fully developed ceramic substrate materials and there is not a large number of suitable substrate supplies on the market.
In recent years, Si deposition on ceramic substrates has almost developed into a standard process.APCVD using SiH Cu as precursor gas at high temperature and atmospheric pressure is the best Si deposition technology.The application of atmospheric deposition process can allow simpler equipment configuration.APCVD deposits a microcrystalline layer on a model substrate or a ceramic substrate. A - Si: H layer of sufficient quality can achieve better ZMR results. Epitaxial thickening and traditional solar cell processing are performed on the ZMR - passed seed layer.Low enough defect density of active layer can make the conversion efficiency of model substrate crystalline silicon thin film solar cell exceed 16 %.The epitaxial layer grown on the ceramic substrate / ZMR seed layer can also achieve comparable quality.However, as mentioned earlier, the stability of the " ceramic substrate / intermediate layer / seed layer" sandwich device structure is a prerequisite for successful epitaxial growth.The results show that the absence of epitaxial growth data can ensure the growth of high-quality MC - Si: H or epitaxial layers on low-quality substrates or seed layers.
ZMR and Si deposition process steps require the development of equipment especially for photovoltaic applications, and the research and development of these equipment has also made important progress.The lack of mature conventional equipment is one of the reasons for the relatively slow process of research and development of heterogeneous substrate crystalline silicon thin film solar UPS BATTERY.However, ZMR equipment developed by FHG - ISE in German Flawn Hoff Solar System Research Institute can handle 400 mm wide samples, which is a major breakthrough in the development of ZMR equipment.Several research teams have also made great progress in the rapid and low-cost Si deposition process for heterogeneous substrate crystalline silicon thin film solar UPS BATTERY, and have all focused on the high-temperature APCVD of Si HCl 3 as the precursor gas.After building samples of Si deposition equipment, the first result confirmed that these equipment can deposit high quality epitaxial layers at high production rates.The development of ZMR and Si deposition equipment can make the sample preparation faster and easier, thus ensuring the better commercial potential of heterogeneous substrate crystalline silicon thin film solar UPS BATTERY.
After the ZMR layer is epitaxially thickened, its structure is similar to that of a conventional polysilicon silicon wafer, so in principle all crystalline silicon solar cell processes can be used.However, if porous ceramics are used as the substrate, it is necessary to improve the solar cell process because higher porosity will cause greater problems in the wet chemical process.Dry process may solve this problem in the future.In the currently developed crystalline silicon solar cell process, a large-scale plasma process for deposition and etching is being developed and commercialized, which is very helpful to the research of heterogeneous substrate crystalline silicon thin film solar UPS BATTERY. The dry process used in traditional crystalline silicon solar UPS BATTERY can be applied to heterogeneous substrate crystalline silicon thin film solar UPS BATTERY only by changing several process parameters.
According to the existing research results and the great potential of improving the conversion efficiency, the heterogeneous substrate crystalline silicon thin film solar cell prepared by high-temperature APCVD and ZMR technology has a good commercial prospect for large-scale production.In order to achieve this goal, research and development needs to focus on:
Suitable solar cell drying process:
performing reliable active layer preparation on the improved substrate;
Increase UPS BATTERY size from 1cm2 to at least 100cm2.
With the increasing energy demand all over the world and people's continuous attention to the impact of traditional energy and environment, new energy technologies such as solar energy have become the hottest high-tech fields.At present, silicon wafer-based crystalline silicon solar cell technology is the mainstream of the market, occupying more than 90 % of the market share.Several thin-film solar cell technologies have also been developed, mainly amorphous silicon thin-film solar UPS BATTERY, copper indium gallium selenium thin-film solar UPS BATTERY and cadmium telluride thin-film solar UPS BATTERY, but these thin-film solar cell technologies still cannot challenge the dominant position of crystalline silicon solar UPS BATTERY, because crystalline silicon solar UPS BATTERY are superior in performance, high in stability, rich in raw materials, safe and nontoxic.This chapter will introduce the thin-film solar cell technology, which has both the absorption layer of crystalline silicon and the structure of thin film, combining the advantages of crystalline silicon solar cell and thin-film solar cell. This is the polysilicon thin-film solar cell technology.
Definition of Polysilicon Film
In polycrystalline silicon solar UPS BATTERY, the English word " polycrystalline silicon" is multicrystaililicon with a grain size of 1 mm 10 cm, while in polycrystalline silicon thin film solar UPS BATTERY, the grain size is defined as 1 / im - l in some documents, while we prefer to define the grain size as 0.1 / im - lmm because some polycrystalline silicon has a grain size of less than 1 mm .." Polysilicon" appearing in this chapter refers to Polycrystaililicon.
The grain size of polycrystalline silicon is much larger than that of microcrystalline silicon ( also called nanocrystalline silicon ) prepared by plasma enhanced chemical vapor deposition PECVD at low temperature ( about 200 C ).Si: H has a typical grain size of several tens of nm and still includes a considerable proportion of amorphous silicon A - Si: H. In fact, the transition region between A - Si: H and - Si: H has the best quality [ 2 ].In contrast, the crystallinity or crystalline fraction of polysilicon is close to 100 %, and the disordered amorphous structure is confined to a very thin and relatively sparse grain boundary region.
As used herein, " thin film" refers to a crystalline layer deposited, rather than a crystalline layer obtained by melt casting or thin layer transfer techniques.Generally speaking, the thickness of polysilicon thin film less than 30 typical is 3103.1.2 development potential
As mentioned earlier, polycrystalline silicon thin film solar UPS BATTERY with great development potential will make full use of the advantages of traditional crystalline silicon solar UPS BATTERY.Si is one of the most abundant elements on the earth, so this technology is suitable for large-scale production.The potential toxic problem is the main obstacle to the development of cadmium telluride thin film solar UPS BATTERY, but it has nothing to do with Si.The stability and reliability of crystalline silicon solar cell modules are by far the most decisive advantages, but the reliability problem has plagued several kinds of thin film solar UPS BATTERY at the initial stage of technological development.Moreover, polysilicon thin film solar UPS BATTERY still have the potential of high conversion efficiency in principle.
Is the polycrystalline silicon thin film solar cell more advantageous than the heterogeneous substrate crystalline silicon thin film solar cell in chapter 2, the microcrystalline silicon thin film solar cell in chapter 4 or the thin layer transfer technology?Among several kinds of silicon-based thin-film solar UPS BATTERY, polysilicon thin-film solar UPS BATTERY seem to be less well-known and do not have much advantages at first sight.The process temperature required for deposition of Si thin film by polysilicon thin film solar UPS BATTERY is much higher than that of microcrystalline silicon thin film solar UPS BATTERY, and the higher the temperature the substrate can withstand, the higher the cost.However, the crystal quality of polycrystalline silicon thin film solar UPS BATTERY and microcrystalline silicon thin film solar UPS BATTERY is much lower than that of heterogeneous substrate crystalline silicon thin film solar UPS BATTERY and monocrystalline silicon thin film solar UPS BATTERY.More importantly, due to the lack of good results, some experts have questioned in the literature whether high-efficiency solar UPS BATTERY can be produced within such a grain size range, even comparing the grain size range of 0.1 mm - lmm to " painful valley bottom" and comparing monocrystalline silicon film and microcrystalline silicon MC - si: h film to " mountain peak" %.The author believes that such a conclusion stems from the wrong interpretation of the data.In fact, there are many examples that bring many hopes to polysilicon thin film solar UPS BATTERY, and it can even be said that polysilicon thin film solar UPS BATTERY are the thin film solar cell technology that is most likely to challenge the dominant position in the crystalline silicon solar cell market.
Although Si is an indirect band gap semiconductor, its ability to absorb human light is relatively weak, in principle, thin films of several thicknesses can also achieve ideal current and conversion efficiency.This is because the light trapping structure can considerably improve the absorption rate 5 ].
The textured surface on the front surface of the Si active layer combined with the back reflector can achieve better light trapping effect.Theoretically, as long as one of the two film surfaces is a Lambertian mirror, the light will be diffusely reflected, and a nearly optimal light trapping structure can be obtained.In fact, diffuse reflection on both surfaces at the same time can achieve the best results.Because of the weak absorption in Si, the light trapping structure is particularly important for light with wavelengths greater than 800N m.
The maximum short-circuit current density obtained by irradiating solar UPS BATTERY with normalized solar spectrum can be used to characterize the efficiency of human light absorption.Assuming that the Si layer thickness is infinite and photo-generated carriers are completely collected, the maximum current density is 47mA / cm2.Similarly, the dependence of the maximum current density on Si film thickness can be calculated and compared with the four cases of 80 % back surface diffuse reflection / 80 % back surface specular reflection and no antireflection film ARC / double layer antireflection film DL ARC.If there is 80 % diffuse reflection of DL ARC and back surface, the maximum short-circuit current density can exceed 30mA / cm2 even for 2 thick films.Because the refractive index of the glass or ceramic substrate is smaller and its reflectivity is generally > 90 %, which is greater than the 80 % back surface reflectivity assumed here, the potential of current should be greater.However,' the calculation here assumes 100 % photo-generated carrier collection efficiency, in fact, the number of carriers collected is smaller and depends mainly on the characteristics of minority carriers.Increasing UPS battery life main failure modes, charging and monitoring solutions
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